FYP2 progress 1
by OOI CHUN WEI
Week 1
Goals & Expected Results
- State the goals of experiment
The goal of this project is to design a base-4 fault tolerant Booth multiplier by using 0.18µm standard CMOS technology. Then characterize and optimize the timing, area and power performance of the base-4 fault tolerant Booth multiplier.
- State the expected results of the project
The expected result of this project is to design the base-4 fault tolerant Booth multiplier with a low power dissipation and area consumption. The fault tolerant Booth multiplier should able to mask the fault and send the correct signal to the output result.
For this week, I have done the Verilog code of two multiplexers which is multiplexer of untested results and inputs multiplexer.
The Verilog code for muxOUT41 module
The Verilog code for mux41 module
Week 2
State how does the test bed/prototype help to achieve the objective of the experimental?
The prototype of this project is to generate a fault tolerant system for four base-4 Booth multipliers. This will help to reduce the chip area consumption and its power consumption.
On 29 Mac 2022, I have attended the Online Research Methodology. The coordinator of FYP showed the guidelines and action plan for the FYP2. The coordinator gave some briefing as well for the FYP2 seminar were planned to be held on 23rd June 2022. He also mentions the demo video need to be submitted before the seminar.
This week, I have finished the Verilog code for the voter module and I am going to start writing the Verilog code for the combination design.
The part of the voter module Verilog code
Week 3
Design Experiment
- Draft the designing of experiment.
The fault-tolerant base-4 Booth multiplier is using the modified triple modular redundancy techniques. Two base-4 test Booth multipliers, two 4-bit 4-to-1 multiplexers, a test module, and a 2-bit synchronous up counter are added to the upper half of the circuit, followed by an 8-bit comparator in the lower half to mask hardware failures and system problems. The four Booth multipliers in base-4 represent four multipliers with various tasks and inputs.
- Will the experiment help to achieve the objectives?
Yes. This experiment was did for achieving the objective of the project. The fault tolerant system can used to correct and replace the output. To reduce the area consumption, a single fault tolerant system was apply for four Booth multipliers. It becomes backup when error happens.
For this week, after meeting with my supervisor, supervisor had suggested to edit my block diagram by adding bus labels to each wires. Besides, I have started to code the combinational design.
Week 4
Initial Data Analysis
The initial data was collected by using Quartus II to obtain the waveform of the base-4 Booth multiplier. When the circuit is complete and implement, the waveform shown should same as this initial data after inserted the stuck-at fault.
The initial data which is the waveform of the base-4 Booth multiplier
For this week, I have edited the block diagram and added the bus labels. Also, I realized that my circuit needs registers and replacement block to adjust the timing problem and replace the final result with the corrected output. Then, I manage to code the register block in this week.
The schematic diagram after added the bus labels for each wires.
The Verilog code for the register module
Week 5
Pitfalls
What are the unsuspected difficulties faced in order to achieve the goals of experiment?
The hardest part is adjusting the timing for each tested and untested outputs in order to get the correct timing position while comparing in the voter module. This can be consider tricky since there is some unwanted output will be show in the waveform before we get the correct one. Therefore, register is needed and the timing need to control carefully.
Another difficulty is to replace the wrong output by correct output. As mentioned above, there is four multipliers but only one fault tolerant system. This means that fault tolerance requires four outputs to be tested in turns. Therefore, the circuit is require to identify which output is wrong and need to replace the correct output to that multiplier.
For this week, I had done the replace module code and continue on the combinational design coding.
The Verilog code for replace module