FYP2 progress 3
by OOI CHUN WEI
Week 10
Construct a table of FYP2 Work Break Down Structure and Milestones.
Table 1: FYP2 Work Break Down Structure and Milestones
|
Task |
Start Date |
End Date |
Remarks |
|
Complete the Verilog code of 4 bits and 8 bits multiplexer modules. |
20/3/2022 |
26/3/2022 |
Quartus II is used to design the module codes. |
|
Design the voter module. |
27/3/2022 |
2/4/2022 |
Quartus II is used to design the module code and obtain its RTL design. |
|
Design the register module. |
10/4/2022 |
16/4/2022 |
Quartus II is used to design the module code. |
|
Design and test the replace module. |
17/4/2022 |
23/4/2022 |
Quartus II is used to design the module code. |
|
Improve the fault tolerant Booth multiplier schematic diagram |
3/4/2022 |
23/4/2022 |
Replace module is added and each wires are added the bus labels. Test module is removed due to timing issue. |
|
Combine and implement the circuit |
3/4/2022 |
30/4/2022 |
|
|
Design the testbench for the combinational circuit |
2/5/2022 |
14/5/2022 |
Waveform and output of the combinational circuit are obtained. |
|
Synopsys tools implementation and performance analysis |
15/5/2022 |
6/6/2022 |
Design compiler (DC), IC compiler (ICC), and PrimeTime (PT) are done to obtain the pre/post-layout of the design and the timing, area and power results. |
|
Fault injection and fault coverage |
7/6/2022 |
18/6/2022 |
To be scheduled. |
For this week, I was focused on the Synopsys DC tools implementation. The constraint and tcl file were coded to source my combinational circuit module Verilog file (BM_Final.v) and other sub modules Verilog files into the dc_shell. Then the Silterra 0.18?m technology process library is used to convert the design into gates netlist. The result of area, timing, and power for the pre-layout design are obtained and the netlist is saved for IC Compiler purpose.
Figure 1: The timing report for DC.
I also wrote the notes for base-2 and base-4 Booth multiplier to justify the different operation and calculation between both of them.
Figure 2: The calculation steps for Base-2 Booth multiplier.
Figure 3: The calculation steps and algorithm table for Base-4 Booth multiplier.
Week 11
Construct a FY2 Gantt Chart
Table 2: Gantt Chart for FYP2
For this week, I had done the IC compiler by using Synopsys tool. The netlist saved in Design Compiler is import to IC compiler for placement and routing. IC Compiler is used for innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure. The graphical user interface (GUI) was obtained from the this process and the post-layout design was saved for PT purpose.
Figure 5: GUI from IC Compiler.
Week 12
Construct a table of PROJECT BUDGET (Cost of material and component)
Table 3: Costing and license rental of the tools
For this week, I continued my FYP in Synopsys PrimeTime implementation. I had coded the PT constraint and tcl files for obtain the area, timing, and power results. Basically, the codes and process are similar to the DC as one of the purposes of undergoes PT is to check the accuracy between pre and post-layout and to prevent the mistake or error happen during routing (ICC). By loaded the post-layout design from IC Compiler, the design specification (timing, area, power and etc.) are obtained and all the timing reports are met.
Figure 6: Timing report for PT.