FYP2 progress 2

Week 6

Lower Order Thinking Skills (LOTS) includes the answer given in the reading.

1. State the theories/algorithm used in this project.

The theory and algorithm that used in this project are radix-4 Booth multiplier algorithm and triple modular redundancy concept. The Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation while the triple modular redundancy (TMR) is a fault-tolerant form of N-modular redundancy, in which three systems perform a process and that result is processed by a majority-voting system to produce a single output.

Figure 1: The Algorithmic state machine (ASM) chart for Radix-4 Booth multiplier.

Figure 2: The encoding table of Radix-4 Booth multiplier.

Figure 3: The design concept of triple modular redundancy.

1. Where are these theories/algorithm being implemented in the project?

The Booth multiplier algorithm is being implemented on the multiple process. The Radix-4 Booth Recoding is being implement to simplify a multiplexor that selects the correct shift-and-add operation based on the groupings of bits found in the product register. The triple modular redundancy is being implemented on fault tolerant system.

For this week, I was finished the combinational design coding. The BM_final module is compile successfully as Figure 5 shown. Schematic diagram also obtained from RTL viewer.

Figure 4: The combinational design code (BM_final module)

Figure 5: The result of compilation.

Figure 6: The schematic diagram that obtained from RTL viewer.

Week 7

Higher Order Thinking Skills (HOTS) includes implicit answers (not boldly stated answers)

1. Explain the outcome(s) of the results. (pattern, sequencing, etc)

The outcome of this project will be successfully reduce the injected faults and replace it with the correct output. The output will display the number of error and malfunction of the system.

1. Compare results with conventional/crude/other existing method.

Explain the relationships/differences.

The initial fault tolerant system can only test a device by adding two extra devices for the voting purpose. However, this will causes the size of system increases and it would be a luxury if TMR fault tolerance was applied to each chip. For this project, the extra devices are share by four devices which require to test. This will helps to reduce the cost and the size of this project.

For this week, I had started to write the testbench code. In order to avoid too many bugs happen, I plan to set the same inputs for the 4 modules. This will allow me to check the correctness of my BM_final module.

Week 8

Higher Order Thinking Skills (HOTS) includes implicit answers (not boldly stated answers).

1. Discuss the implementation of the end product of the project.

The implementation of the end product would be an ASIC design with eight different inputs for multiplication purpose. Its fault tolerant system will be apply to correct the output when there is a fault occurs in a device.

This week, I have coded the testbench code. In order to get a variety of different inputs, nested for loop was applied to control and change the values of multiplier and multiplicand. However, there are still some bugs to fix. Then I meet with my supervisor to clarify about the concept of radix-4 for Booth multiplier.

Figure 7: Part of Verilog testbench for this project.

Week 9

Higher Order Thinking Skills (HOTS) includes implicit answers (not boldly stated

answers)

1. Discuss the future improvement of the project.

There are some improvement that can be suggested to increase the performance and fault coverage of this project. First of all, the self-test system can be added to improve the fault coverage percentage. But the side effect is that this leads to a larger chip area and will cause a lot issues. The second improvement is to reduce the time consumption by changing the radix-4 Booth multiplier to radix-8 or higher. But at the same time, the complexity of the design will also increase, and may lead to a price-performance mismatch

For this week, I started writing the Design Compiler (DC) codes. It takes me some time to recall my Synopsys knowledge. Therefore, I will be mainly focus on researching and studying the Synopsys code for DC, IC Compiler (IC) and PrimeTime (PT) programming. Synthesis is one of the function in Design Compiler (DC). It is the process of transforming the HDL design into a gate-level netlist, given all the specified constraints and optimization settings. Logic synthesis is the process of translating and mapping RTL code written in HDL (such as Verilog or VHDL) into technology specific gate level representation. Therefore I need to use DC to convert my Verilog code to logic design. Besides, I also meet with my supervisor this week and we discuss about the function of encoding table for radix-4 Booth multiplier and the difference between the calculation methods for radix-4 and radix-2 Booth multiplier.