FYP2 ENTRY 2: Reflection of progress 2 - CHEW CHOON SENG

Week 6

Lower Order Thinking Skills (LOTS) includes the answer given in the reading.

1. State the theories/equations used in this project.

There are few equations that needed to apply to this project for the pre-processing phase of the Pan-Tompkins algorithm.

Low pass filter’s difference equation:

y(n)=2y(n-1)+y(n)+x(n)-2x(n-6)+x(n-12)

High pass filter’s difference equation:

z(n)=z(n-1)-y(n)/32+y(n-16)?y(n-17)+y(n-32)/32

Derivative filter’s difference equation:

j(n)=1/8[2z(n)+z(n-1)-z(n-3)-2z(n-4)]

Square process equation:

s(s)=s(n) x s(n)

Moving window integrator equation:

S(n)=1/32[s(n-32)+s(n-31)+...+s(n)]

Heart rate equation:

Bpm = 60/RR(s)

2. Where are these theories/equations being implemented in the project?

These equations are being implemented on the pre-processing phase of the Pan-Tompkins algorithm for the noise cancellation. After the pre-processing of the ECG signal, decision rules is also needed to implemented in order to detect a QRS complex. Lastly, once the QRS complex is successfully recognize, the heart rate is computed as a function of the distance in second between two consecutive QRS complexes.

For this week, my FYP progress was continued with the Verilog code design of the decision rules process. This decision rule process is required in the project design to detect the QRS complex after the pre-processing phase of the Pan-Tompkins algorithm.

Decision rules schematic diagram

Week 7

Higher Order Thinking Skills (HOTS) includes implicit answers (not boldly stated

answers)

1. Explain the outcome(s) of the results. (pattern, sequencing, etc)

The outcomes of the results for the Verilog design are expected to have the peak location of the QRS complex, peak values of the QRS and also the bpm values after a samples are loaded in to the design.

2. Compare results with conventional/crude/other existing method.

Explain the relationships/differences.

The outcomes should be the same with other existing products to detect the QRS complex and also the bpm after samples are loaded in. However, if compared to the computation time it can be confirmed that this project will be much faster than other existing products due to ASIC implementation and ASIC are designed for a specific purpose rather than for general-purpose methods designed products.

For this week, my FYP progress was continued by designing the top function of the Verilog design. Inside of the top function scripts, all of the Verilog design of low pass filter, high pass filter, derivative filter, squaring process, moving window integrator and decision were instantiated as lower-level modules to obtain the whole Pan-Tompkins algorithm for QRS complex detection.

Instantiated the lower-level modules of LPF, HPF, Derivative, Square Integration and Decision

Top level schematic diagram

Week 8

Higher Order Thinking Skills (HOTS) includes implicit answers (not boldly stated

answers).

1. Discuss the implementation of the end product of the project.

The implementation of the end product is the user should load in the clock, ECG samples, and also the reset into the ASIC design. After loading in these inputs, the output should come out the QRS complex location, QRS complex peak values, and also the bpm of the ECG signal.

For this week, my FYP progress was continued by designing the Verilog testbench code for the project design.

Verilog testbench for the project design

The method that I used to load in the sample of ECG data is using the $readmemb function and this function is to read the vectors that stored inside of the arr.txt file. Therefore, the vectors could be read in the array and applied to the DUT.

Week 9

Higher Order Thinking Skills (HOTS) includes implicit answers (not boldly stated

answers)

1. Discuss the future improvement of the project.

There are few of the improvement and modification to enhance the current work project. Firstly, the design should also have the analog to digital conversion so that the real-time ECG can be used as the input for the QRS complex detection. To ease the work in this project, only the prepared ECG data is loaded in for signal processing. Secondly, the project should also be applied into the FPGA first before the VLSI and ASIC design to make sure that the hardware functionality of the project is correct.

For this week, my FYP progress was continued on studied on the Synopsys tools which include of Design Compiler, IC Compiler and also PrimeTime. By using the Design Compiler, it can constraint the design for customize areas and timing and also provide an optimal gate-level synthesized netlist based on the design specifications. For IC Compiler it is used to perform the physical design on designs with moderate congestion and timing challenges. For IC compiler flow is Data Setup ->Design Planning -> Placement -> Clock Tree Synthesis -> Routing -> Design for Manufacturing. Lastly for PrimeTime is actually to generate and interpret timing reports, create a clean, optimized run scripts and debug timing violations.