FYP2 ENTRY 3: Reflection of progress 3 - CHEW CHOON SENG

Week 10

Construct a table of FYP2 Work Break Down Structure and Milestones.

Figure 1: FYP2 Work Break Down Structure

In this week, my FYP progress was continued with Synopsys DC tools implementation. For the data setup process, I had loaded in the RTL hardware design, constraints file and also the standard library cell into the DC tools to translate the design into a gate-level netlist. For the overall design, Silterra 0.18 µm technology process library is being used to convert the design into a technology-specified gates netlist. The design constraint for the RTL synthesis in the field of area, timing and environmental attributes are prepared and loaded in the synthesis process. All of the reports are generated from the DC and it seems that all the violations are allowed in the design.

Figure 2: GUI of Design Compiler

Week 11

Construct a FYP2 Gantt Chart

Figure 3: FYP2 Gantt Chart

For this week, my FYP progress continued with Synopsys ICC tools to perform the operations with moderate congestion and timing challenges on the designs. The main physical design steps are data setup, design planning, placement, clock tree synthesis, and routing. For data setup, the same library setup as in DC needs to be performed for logic libraries as logic libraries will provide the information of the standard cells such as timing, design rule constraints and power consumption. The information such as resource utilization, area, timing critical path delay and congestion can be found in the reports that generated from ICC and it seems that all the violations are allowed in the design.

Figure 4: GUI of IC Compiler

Week 12

Construct a table of PROJECT BUDGET (Cost of material and component)

Figure 5: Costing of Materials and Tools in this project

For this week, my FYP progress continued with the last part which is the Synopsys Prime Time. It is a static time analysis (STA) that verifies a gate-level circuit's timing using SPICE characterized data kept in a technology library. Therefore, PT can perform a more accurate power and timing analysis compared with DC and ICC. The reports that generated from the Prime Time are observed to make sure the timing constraints are met. This is because if the time constraints is not met, it means that the flip flop in the design will enter the metastable state which means the output generated will not similar as the expected design.