FYP2 ENTRY 1: Reflection of progress 1 - CHEW CHOON SENG

Week 1

Goals & Expected Results

• State the goals of the experiment.
• To develop and design an ASIC-based IIR filter for QRS ECG Signal Detection using 180nm CMOS technology.

• State the expected results of the project.
• The experiment will be using two different software which are MATLAB software and VCS software. The purpose of using MATLAB software is to show that the design of the IIR filter for Pan Tompkins QRS ECG detection is functionally well after loading in a sample of ECG data. Besides, the VCS software was also used to verify the functionality of the Verilog design by investigating the waveform output after the simulation. The output of the graph results collected from MATLAB should show the frequency and also the location of the QRS complex of the loaded data. Besides, the results collected from VCS should be the same with MATLAB to prove that the Verilog design is correct. For ASIC design, there should be have three main signal input pin which are ecgi, clk and reset. Besides, there should also have two main signal output pin which are outecg_loc and ecgo. For outecg_loc it indicates the location of the R-peak in ECG signal which is the most important part to identify ECG disease or status in a person.

Week 2

State how does the test bed/prototype help to achieve the objective of the experimental?

• When designing something new, with lots of unknowns, we build prototypes to answer questions. Prototype experiments are a way of ensuring that the questions we want answered are clear. Besides, a prototype is also important in reminding us about the objectives and the goals that we want to achieve in the experiment.

On 29 Mac 2022, I have attended the Online Research Methodology. The coordinator of FYP showed the guidelines and action plan for the FYP2. Some briefings have been given as well for the FYP seminar which is planned to be held online on 23rd of June 2022, and a video demo had to be recorded and submitted before the seminar.

For this week, my FYP progress was continued by starting to code for the Verilog design of LPF and HPF.

LPF schematic diagram

HPF schematic diagram

Week 3

Design Experiment

1. Draft the designing of experiment.
   1. For the Pan Tompkins algorithm of ECG QRS complex detection, there are few pre-processing needed to be executed which are low-pass filter, high-pass filter, derivative filter, squaring and moving window integration. Therefore, by using Matlab software, these pre-processing are being designed. After verifying the correctness, it is also been designed in Verilog code for chip design. Lastly, Synopsys software will also be used for ASIC design to show the area size, average power, timing and total cells of the design.

2. Will the experiment help to achieve the objectives?
   1. From the experiments, it helps in developing and designing an ASIC-based IIR filter for QRS ECG Signal Detection using 180nm CMOS technology. Besides, it also helps to analyze the performance of the ECG QRS complex detector using Synopsys for ASIC design.

For this week, my FYP progress was continued by starting to code for the Verilog design of the Differentiation filter and squaring.

Differentiation filters schematic diagram

Squaring schematic diagram

Week 4

Initial Data Analysis

From the initial data that collected from Matlab, for the LPF, the graph shows smoother compared with the initial loaded in ECG data. This is the same for the HPF because both of these filters will filter out the noise of the ECG signal. For the other signal processing, the output of the results are also been verified for its correctness of functionality.

Week 5

Pitfalls

What are the unsuspected difficulties faced in order to achieve the goals of experiment?

1. The first difficulty is in initially, the hardware design will be coded in Vivado HLS by C programming and after testing and debugging in Vivado HLS software, the RTL code should be exported from it. However, due to some unknown errors occurred, the exported RTL is not suitable for further use in Synopsys software. Therefore, the RTL code had designed on my own which actually becomes the most challenging part in this experiment.
2. The second difficulty is the VNC viewer problem. In Windows OS, sometimes it will occur some errors causes unable to remotely control the laboratory PC. It is required to use the laboratory PC for Synopsys tools due to the high costly of its licenses. Therefore, the ways to solve the problem is using the Linux OS and opening the software of Remmina which is same functionality as VNC viewer.

For this week, my FYP progress was continued by starting to code for the Verilog design of the moving window integrator.

Moving window integrator schematic diagram