FYP1 Progress 1

Week 1

After my internship, I chose "Design and characterisation of base-4 booth multiplier for fault tolerant test" from a list of potential projects provided by my intern supervisor for my final year project. These are some of the questions that I answered based on the summary list of activities.

Why is this a project to begin with?

• As the scaling of the device density increases rapidly, the fault-tolerant system becomes more and more crucial, especially in nanoelectronic devices. Fault-tolerant architecture plays a important role in the safety and mission-critical application such as space and medical application. These applications require high reliability to maintain continuous operation without fault.

What are the things you want to improve?

• The improvement that could be made in future is to optimize the integrated circuit to overcome the Kogge-Stone Adder limitation.

Week 2

I attended the Online Research Methodology Workshop. The workshop briefly mentioned in the beginning that there was a separate YouTube video link on Research Methodology conducted by UTM last year that we can watch. The remainder of the workshop talked about the Innovate Malaysia Design Competition. Besides that, in order to ensure the project is on the right track, I have set the goals and major deliverables/contributions to this project.

What are the goals of your project?

• To develop a 4-bit booth multiplier for fault tolerant test.

What are the major deliverables/contributions of this project?

• To develop a fast booth multiplier with the method of fault-masking and fault tolerance for softening the impact of nanotechnology and soft error to the life-critical applications.

Week 3

To promote a smoother project flow, the following questions were addressed in order to gain a better understanding of the project.

What purpose does the work serve, what is the end-goal?

• The purpose of the work serve is to get a better performance of a system for fault tolerant test.
• The end-goal would be designing a fastest booth multiplier (more than radix 4) with the smallest size and lowest power consumption.

What should be done at this early stage to ensure fewer risks and obstacles during the course of the project?

• Understand the definition and function of fault tolerant test.
• Study on the concept of base-4 booth multiplier.
• Study on other articles to get the idea of designing the project.
• Search for the Verilog code of the Kogge-Stone Adder fault tolerant system.

What are the major steps in the project plan?

• Identify a suitable method to develop a base-4 booth multiplier for fault tolerant test.
• Design a base-4 booth multiplier as a fault tolerant system.
• Characterize and optimize the performance of base-4 booth multiplier.

The FYP 1-0 (a) Topic Proposal Form that I have filled based on the valuable advices from my supervisor, Madam Norhafizah.

Week 4

There are some interesting problems regarding to this potential research. Based on some articles that I read, I have summarized three major problems for my research.

1. Area and power consumption for base-4 booth multiplier.
2. The limitation of fault tolerant parallel prefix adders.
3. The trade-off rate between the fault masking rate and ASIC performance.

Write a possible research question for each of the above problems.

• How to reduce the area and power consumption for base-4 booth multiplier?
• What is the limitation of the fault tolerant parallel prefix adders such as Kogge-Stone Adder?
• How to determine the fault masking and control trade-off rate between the fault masking rate and ASIC performance?

Write possible hypothesis for each of the above research questions.

• Design a small or middle performance of the base-4 booth multiplier.
• Fault tolerant parallel prefix adders will have little overhead of area and power performance.
• Try to further optimized the fault tolerant parallel prefix adders then apply it in booth multiplier.

Week 5

To get some background information on how others have tried to design the fault tolerant test, research papers are searched based on 2 categories:

• Papers that tried to accomplish the design of fault tolerant by using adder.
• Papers that tried to accomplish the design of high performance base-4 booth multiplier.

For this week, I have reviewed 5 different papers related to design of fault tolerant and booth multiplier topic.

In one article titled 16-bit Fault Tolerant Sparse Kogge Stone Adder using 0.18?m CMOS Technology, Chang Chin Kai et al. (2020) stated that the tremendous increase in the integration density and the downscaling of the nanotechnology cause the system exposed to the soft error more frequently. Therefore they developed a 16-bit fault tolerant sparse Kogge Stone Adder (KSA) by implementing Triple Modular Redundancy (TMR) approach. The results show that the fault tolerability had been greatly improved at almost double the masking rate of the adder alone and can be operated at the maximum frequency of 166.67 MHz.

In another article, Improved Fault Tolerant Sparse Kogge Stone Adder, Mangesh B Kondalkar et al. (2013) mentioned that a fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry tree but no error detection is possible. Besides that, they had introduced several enhancements in their design such as the error recovery time is reduced by using a 16-bit register, error correction due to fault in multiple ripple carry adders is included which improves the reliability of the circuit. The power analysis and the timing analysis for the estimation of setup time and hold time is also performed.

In the third article titled Towards fault tolerant parallel prefix adders in nanoelectronic systems, Wenjing Rao and Alex Orailoglu (2008) had focused on the fault tolerance of high performance parallel prefix adders (PPA), and exploit the inherent redundancy in PPAs to develop efficient fault tolerance approaches. Based on the particular regular structure of PPAs, an online diagnosis scheme can be developed, thus enabling the application of reconfigurability of nanoelectronics for the highly flexible online repair approaches. Thus, in contrast to traditional fault tolerance techniques that rely solely on significant external overhead, the proposed approach opens up a new genre of efficient fault tolerance techniques for arithmetic components in the nanoelectronic environment.

In the fourth article titled Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA, Anis Shahida Mokhtar el at. (2021) presented the performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is 20.78 ns.

In the fifth article titled Design and Implementation of Compact Booth Multiplier for Low power, Low Area & High Speed Applications, Sivakumar Murugesan el at. (2017) design a compact booth multiplier by using modified radix4 recoding and an efficient finite state machine (FSM) to achieve small chip size and low delay utilization. In the existing technique, compression based booth multiplier is designed by using carry look ahead adder, multiplexer, booth encoder and partial product generator (PPG). It requires more resource utilization (area) and the performance characteristics is very less in the existing booth multiplier. To come up with a solution to this problem, modified radix4 algorithm with an optimized FSM design is used to construct the compact booth multiplier. Simulation and synthesis is performed by applying the ModelSim and Xilinx 13.1 based on Verilog HDL.

From these articles, one common idea is that almost of the researches are related to the design of fault tolerant adders with the target of small area, low power consumption and high performance. But, it seems like none of the research is relate to the design of booth multiplier for fault tolerant test. Therefore, my research might become a new start of that field.