FYP Progress 2

Week 6

• Accurate and Factual Information Supported by Evidence (Refereed journals or publications are the ones that contain information reviewed by several experts in the field)
  • Does the information you have located come from authoritative sources?
  • If you obtained the information from a web site, how reliable is the information?

In terms of the information obtained, the papers had some acknowledgments. For example, the paper titled 16-bit Fault Tolerant Sparse Kogge Stone Adder using 0.18μm CMOS Technology was partially supported by the Ministry of Education Malaysia (MOE) and Research Management Centre (RMC) of Universiti Teknologi Malaysia.

The majority of the papers I obtained came from IEEE websites, and I believe the information is trustworthy because the majority of the papers came from the IEEE Xplore website, which is a research database for finding and accessing journal articles, conference proceedings, technical standards, and related materials on microelectronic, electrical engineering and electronics, and allied fields.

• The Timeliness of the Publication. (For very current info then timeliness is a must but for historical perspective then timeliness may not be crucial)
  • Is the information timely or out-of-date for your topic?

In terms of publishing timeliness, the chronology spans from the 2008s to the present. As a result, the material is still deemed timely.

• Type of Publication (This indicates different levels of complexity in introducing ideas)
  • Is the source scholarly, popular, trade or government publication?

In my opinion, most of the sources are scholarly, because these papers are completed by other universities that implement similar concepts.

For this week, I have reviewed 2 different articles related to booth multiplier topic.

In the first article, Design of an Efficient High Speed Radix-4 Booth Multiplier for both Signed and Unsigned Numbers, A.S.Prabhu and V.Elakya (2018) designed an efficient High speed Radix-4 Booth multiplier for both signed and unsigned numbers. The Proposed Booth multiplier is the capable multiplier which treats both positive and negative number consistently dissimilar to conventional multiplier. To obtain better performance, they minimize the number of addition which in turn reduces the number of partial product. The efficient algorithm that will minimize the number of multiplicand is Booth algorithm. It has been proved that it can be useful to apply the proposed Booth architecture in high speed multipliers because of the gain in time obtained due to reduction of partial products to k/2. The proposed multiplier increases the speed by 62.411% than the Array multiplier with almost same area (LUTs).

In the second article titled Design and Implementation of Radix-4 Based High Speed Multiplier for ALU’s using Minimal Partial Products, S. Shafiulla Basha el at. (2012) provided the methods required to implement a high speed and high performance parallel complex number multiplier. The designs are structured using Radix-4 Modified Booth Algorithm and Wallace tree. These two techniques are employed to speed up the multiplication process as their capability to reduce partial products generation and compress partial product term by a ratio of 3:2. Despite that, carry save-adders (CSA) is used to enhance the speed of addition process for the system. The system has been designed efficiently using VHDL codes for 8x8-bit signed numbers and successfully simulated and synthesized using Xilinx.

Week 7

There are several tests this week, and since I have to focus on my subject tests and the revision of these tests, therefore I only listed some relationships between the potential and frequency of use of the proposed ideas.

• List the relationship of proposed idea to the system/end user/stakeholder in terms of daily or routine use.

System – Computing system – A booth multipliers is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers.

• List the relationship of proposed idea to the system/end user/stakeholder in terms potential.

Fault-tolerant multipliers with low power consumption are the need of today’s computing systems. So this proposed idea can help to solve the power dissipation and heat removal problem for all battery-powered electronic systems.

• List the relationship of proposed idea to the system/end user/stakeholder in terms of frequency of use.

Multipliers are most commonly used in various electronic applications. Therefore, this booth multiplier may frequently use thousand times per day.

Week 8

For this week, I have reviewed 2 different articles related to booth multiplier topic.

In the first article titled Design and Implementation of 256*256 Booth Multiplier and its Applications, G S Surabhi el at. (2020) designed a booth multiplier which performs both signed and unsigned multiplication. They described the implementation of 256-bit booth multiplier by comparing it with 64-bit and 128-bit booth multipliers. The proposed multiplier will be designed and verified using modalism with Verilog HDL, Xilinx is used for synthesis.

In the second article, Designing of a Reversible Fault Tolerant Booth Multiplier, stated that Md. M. Rahman el at. (2018) had designed a reversible fault tolerant booth multiplier which can multiply both signed and unsigned numbers. The proposed circuit tolerant designed using only fault tolerant reversible gates. Thus the entire scheme inherently becomes fault tolerant.

Week 9

During this week, I had a meeting with my supervisor, she had suggested to change my FYP title. Due to some consideration, I had decided to change my FYP title to Fault Tolerant Radic-4 Booth Multiplier.

So for this week, I have reviewed 2 different articles related to fault tolerant booth multiplier topic.

In the first article titled Design of Fault Tolerant Multiplier Using Self checking adder and GDI Technique, Mary Swarna el at. (2021) designed 4- bit multiplier utilizing a fault-tolerant one-bit full adder circuit which can identify and repair both transient and permanent faults. Fault-tolerant one-bit full adder is designed using self- checking adder circuit to check any fault and repairing circuit to repair the fault. Further, the utilization of the GDI (Gate Diffusion Input) technique reduces the number of transistors is utilized contrasted with regular full adder circuit thereby reducing the area, power, and delay utilization. This design brings about much lower equipment when compared to the conventional methods. Moreover, the proposed method gives both error detection and correction effectively when contrasted with the current designs.

In the second article, A General Fault Injection Method Based on JTAG explained that JTAG-based fault injection of core devices is a real-time, easy-to-control, non-destructive fault injection method. However, JTAG signal voltages of core devices produced by various chip manufacturers are different, and JTAG instruction codes are also different. Currently, there is a lack of generic JTAG-based fault injection device and method. Therefore, a general fault injection system based on JTAG and a fault injection method are proposed for this problem.