Internship Assigned Task 2 | Skyechip Internship by KUNG CHUN YI

FIFO Design Task

During my internship at Skyechip, my primary task was to design an industry-standard FIFO (First In, First Out) component using System Verilog. The design specifications from my supervisor aimed at creating a FIFO that could buffer and synchronize data between different clock domains or processing units in digital systems.

Through this task, I not only gained proficiency in System Verilog and FIFO design principles but also learned the importance of team collaboration, refinement, and verification using tools like VCS and DVE.