Internship@Skyechip
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The internship at Skyechip has been a unforgettable experience that significantly enhanced my understanding of NoC (Network on Chip) design and RTL (Register Transfer Level) development. Over the course of the internship, I gained hands-on experience with a wide range of tasks and tools that are essential in the IC industry.
From the outset, the onboarding process provided a solid foundation for my journey, introducing me to the company's culture and operational protocols. The initial weeks focused heavily on setting up the necessary development environments, allowing me to familiarize myself with critical tools like the Virtual Network Computing (VNC) compute engine and the DVE software. This foundational work facilitated my learning of Verilog and System Verilog, enabling me to code complex designs such as multipliers and memory components.
As I progressed, my involvement in designing and debugging FIFO components allowed me to apply theoretical knowledge in practical scenarios, enhancing my problem-solving skills. The experience of clearing lint errors in the RTL code helped me understand the importance of code quality and maintainability, which are vital aspects of successful hardware design. Additionally, attending regular team meetings and technical discussions enriched my collaborative skills, providing insights into project dynamics and fostering a strong sense of teamwork.
The latter part of my internship emphasized low-power design principles, where I learned about critical optimization techniques necessary for modern integrated circuits. This knowledge is particularly relevant as industries increasingly prioritize energy efficiency in their designs. The exploration of power gating and voltage scaling methods further solidified my understanding of how to address challenges in low-power IC design.
Overall, my internship at Skyechip not only provided me with valuable technical skills but also helped me grow as a professional. I am grateful for the mentorship and support from my company supervisors, Mr Ngo Gia Thuyet, seniors and NoC team colleagues, which significantly contributed to my development. This experience has inspired me to pursue a career in semiconductor design and has equipped me with the foundational knowledge and skills to excel in this field. I look forward to applying what I have learned as I advance in my academic and professional journey.
Internship Detail
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Company's name: SKYECHIP SDN BHD
Company’s address: 18-12, SUNTECH@PENANG CYBERCITY, 11950 BAYAN LEPAS,
PULAU PINANG MALAYSIA
Company Supervisor’s name: NGO GIA THUYET
Department/unit: FRONTEND DESIGN
Principal activity of company: NoC (Network on Chip)
Student’s scope of work: Learn basic knowledge of digital design
internship Period: 22/7/2024 - 11/10/2024
Company Info
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SkyeChip is a Malaysia based design company dedicated to deliver cutting edge IP & IC solutions for artificial intelligence and high-performance computing. The company is founded in 2019 by a group of world class IC designers with average experience of more than 15 years in MNCs including Intel, Altera, Broadcom, Spansion, Motorola, etc.
SkyeChip has in-depth and complete technical expertise to develop advanced IP and ASIC products, including architecture, micro-architecture, logic design, circuit design, DFT, physical design, layout, test and product engineering. In addition, the SkyeChip team also has extensive experience in project management, new product introduction, and management of global supply chain for volume production.
Mission
- We are at cutting edge technology.
- We aren’t working on yesterday’s problem.
- We are innovating today to provide a solution for tomorrow’s problem.
Vision
We Innovate to Accelerate AI and High Performance Computing
Internship Assigned Task 2
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FIFO Design Task
During my internship at Skyechip, my primary task was to design an industry-standard FIFO (First In, First Out) component using System Verilog. The design specifications from my supervisor aimed at creating a FIFO that could buffer and synchronize data between different clock domains or processing units in digital systems.
Through this task, I not only gained proficiency in System Verilog and FIFO design principles but also learned the importance of team collaboration, refinement, and verification using tools like VCS and DVE.
Industrial Training Job Scope
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Industrial Training Job scope
Interconnect IP Coherent/Non-Coherent Network-on-Chip
- Provide solution lint warnings and errors
- Design and construct FIFO
- Include obfuscation into RTL code
- Learn System Verilog & basic of NoC
Study low power design and optimization in IC design
Internship Assigned Task 1
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Study the Fundamental of System Verilog
This task basically allows me to learn various type of rules and function in System Verilog. All the basics in System Verilog like types of always block, coding style to prevent latches and priority encoder, synthesizable rules and operators, rules for combinational and sequential blocks, FSM design techniques, types of arrays, assertion writing, various type of port instantiation and others. Training materials are provided by Skyechip.
Internship Assigned Task 3
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Learn the Basic of Network-on-Chip
I have learned the basics of NoC architecture, gaining insights into routing algorithms, packet-switching methods, and ARM AMBA protocols, specifically APB and AXI, which are vital for modern IC design. I have dived deep into APB and AXI to learn how they perform read and write operations as in Picture, their differences, and when to use them. At Skyechip, I had the chance to read and learn how to code AXI and APB.
In summary, these NoC components work together to enable high-performance, scalable communication and data management, ensuring efficient operation and resource utilization. Yet there are much more components in the NoC RTL design for to learn in the future if I ever have the chance to work in Skyechip again. Through this task, I have a clear overview of what is network on chip, how does it work and where does it work.
Internship Assigned Task 4
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Obfuscation
The task of obfuscating the RTL code was carried out based on the requirements provided by the senior, with the goal of ensuring that customers can only access the parts of the code they are allowed to view. Obfuscation in RTL (Register Transfer Level) refers to techniques used to deliberately obscure or alter the structure of the RTL code without changing its functionality. The goal is to make the design more difficult to understand or reverse-engineer, thereby protecting the intellectual property (IP) of the hardware design
Internship Project
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Lint Warning and Error Resolution Task
I was assigned a project to resolve lint warnings and errors in the NoC (Network on Chip) RTL code during my internship at Skyechip from week 5 to week 11. This task was critical for ensuring the quality, reliability, and functionality of the NoC design, as lint warnings and errors can lead to bugs, inefficiencies, synthesis issues and potential system failures in hardware implementations.
The primary objective was to identify and resolve lint warnings & errors across multiple RTL modules of the NoC. The errors ranged from basic code structure issues. These errors needed to be systematically addressed to improve the overall robustness of the NoC design. To tackle this task, I used lint tools like VCStatic and Spyglass to analyze the RTL code and check for specific errors and warnings. The project involved identifying and fixing various types of lint warnings.
Through this project, I gained extensive experience in RTL debugging and lint analysis, along with a deeper understanding of how clean, efficient code is essential for NoC designs. Teamworking also very important as I divide the workload with the other intern and constant follow up with to speed up the task completion time. Resolving these lint errors not only improved the functionality of the NoC system but also reinforced the importance of verification and collaboration in the design process. This project was an invaluable learning experience, providing me with hands-on problem-solving skills and a thorough understanding of RTL code optimization in large-scale digital designs.
Summing Up
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This internship has been a crucial step in my career development, and I am grateful for the opportunity to learn and grow at Skyechip.
I would like to express my sincere gratitude to all those who supported me during my internship at Skyechip. This experience has been invaluable in shaping my understanding of the semiconductor industry and enhancing my digital design skills.
First and foremost, I would like to extend my heartfelt thanks to my supervisor, Mr. Ngo Gia Thuyet, for his guidance and mentorship throughout my internship. His insights into the design processes in the Network on Chip (NoC) department were instrumental in helping me develop my understanding of the concepts and practices in this field.
I am also grateful to the entire NoC team for their support and encouragement. Their willingness to share their knowledge and expertise created a collaborative environment that significantly enriched my learning experience. Special thanks to Jia Jian, Denise, Juin Ming, Chong Yam, Ming Wei and Zhen Yin seniors, Yu Ying senior architect whose feedback and suggestions during team meetings helped refine my work and improve my designs.
Finally, I would like to thank my university supervisor, Dr Ooi Chia Yee for her recommendation and guidance support throughout my internship journey. Her belief in me motivated me to strive for excellence in every task I undertook.