Reflection on SCSR1013
At the first glance, The title of the subject itself surprised me. The first think that across my mind was, "Are we really will learn about Logical Gate for the whole semester?" . After our lecture, Dr Raja Zahilah explained to us about the course outline, I know that this subject will be interesting as it are new things for me.
The first 2 subtopics, Digital Logic Overview and Number Systems and Codes, briefly explained about how the digital logic in our daily basis and in industrial . it also heavily emphasized the crucial part about Digital Logic, Binary number system.
Chapter 3, 4, and 5 are fundamental topic in this subject. Chapter 3 are mainly about the function and overview of each logic gates available such as AND gate, XOR gate and X-NOR gate. chapter 4 are more to theoretical lesson which was Lawas and Rules of Boolean Algebra. In this chapter, we learn about Combination logical representation and SOP, POS through K-Map condition.
in a conclusion, Digital Logic are one of my favorite subject in my first year of degree. Although sometimes it gets difficult, but to me it was a challenge to myself to push myself harder to strive better.
Mini Project
DEDICATION & ACKNOWLEDGEMENT
First and foremost, we have to thank and show our gratitude to our lecturer, Dr Raja Zahilah Binti Raja Mohd Radzi. Without her assistance and dedicated involvement in every step throughout the process, this paper would have never been accomplished. Her teaching style and enthusiasm for the course made a strong impression on me and I have always carried enthusiastic spirit during our classes. I would like to thank you very much for your support and understanding over this semester.
Furthermore, we must also thank our friends for giving us supportive advice and also the morale supplements in order to keep up on our work. Getting through our project required more than academic support, and we have many, many people to thank for listening to and, at times, having to tolerate us over the project period.
Last but not least, we would like to give a token of appreciation to our teamwork in finishing this project. We succeed in bonding our own chemistry and performing a great communication on each other throughout the project. We gain a massive satisfaction and experience by doing our project in our own way.
DESIGN OF THE 3-BIT XEROX MACHINE IN DEEDS
(A) In this section, there are 3 main vital components to build a synchronous counter;
- 3 input switch
- 3 JK flip-flop
- Clock generator
3 input switch act as labelled above. Two switch as PRE & CLR switch for all flip-flop.
To start the counter, both of the switch need to set to HIGH (1). To reset the counter, CLR switch need to set to LOW (0) and set again to HIGH (1) to allow counting begin. One switch will always set to HIGH (1) because based on Figures 1.1, the JK of first flip-flop are always in HIGH (1) state.
Next, JK flip flop are fundamental component to do a counter. Figures 1.1 show how the each of JK input are being constructed.
Furthermore, Clock generator are being set as general clock for all the JK flip-flop because this is synchronous counter. Table 1.2 show how counting works in counter by clock generator
|
CLOCK PULSE |
Q2 (MSB) |
Q1 |
Q0 (LSB) |
|
INITIAL |
0 |
0 |
0 |
|
1 |
0 |
0 |
1 |
|
2 |
0 |
1 |
0 |
|
3 |
0 |
1 |
1 |
|
4 |
1 |
0 |
0 |
|
5 |
1 |
0 |
1 |
|
6 |
1 |
1 |
0 |
|
7 |
1 |
1 |
1 |
TABLE 1.2
(B) In this section;
- the input switch (A0, A1, A2) act as 3-bit input that user will have entered. It represents 0-7 in 3-bits. All of the switches will be connected to comparator (B0, B1, B2)
- The comparator has two 4-bits sections that will compare each of the bits separately. A0 will compare with B0, A1 with B1, A2 with B2, but for A3 and B3 the input are always set to LOW (0) because A3 and B3 are MSB for the 4-bit. The reason is because in this project, we only compare 3-bits input switch with 3-bit counter. So the MSB of each comparator section need to set LOW (0) to make sure it will not have any problems in comparing later.
- The output of the comparator, are connected with AND Gate. the AND gate are connected with clock generator. This act as Clock Disabler. Table 1.3 shows how the Clock generator function.
|
CLK |
X |
X’ |
Y |
Y’ |
EXPLAINATION |
|
1 |
1 |
0 |
0 |
1 |
CLOCK ENAB |
|
1 |
0 |
1 |
1 |
0 |
CLOCK DISABLE |
(X = output comparator, Y = output of AND gate)
TABLE 1.3
- From table 1.3, when (CLK * X’) == 1, the clock will be LOW (0). This will prevent from the counter from counting up.
WinCUPL CODING
Name project 4 2018 ;
PartNo 00 ;
Date 12/12/2018 ;
Revision 01 ;
Designer Engineer ;
Company FC UTM SKUDAI ;
Assembly None ;
Location ;
Device gal22v10 ;
/* INPUT PINS // COMPARATOR */
PIN 5 = A0 ;
PIN 6 = A1 ;
PIN 7 = A2 ;
PIN 9 = B0 ;
PIN 10 = B1 ;
PIN 11 = B2 ;
/* INPUT PINS // COUNTER */
PIN 1 = clk ;
PIN 2 = reset ;
PIN 3 = preset ;
pin 4 = start ;
/* OUTPUT // COMPARATOR */
PIN 15 = H ;
PIN 16 = L ;
/* COMPARATOR COMPARING */
H = !(A0 $ B0) & !(A1 $ B1) & !(A2 $ B2) ;
L = !(!(A0 $ B0) & !(A1 $ B1) & !(A2 $ B2));
/* OUTPUT COUNTER */
PIN 20 = Q0 ;
PIN 21 = Q1 ;
PIN 22 = Q2 ;
/* 3 BITS COUNTER DEFINE */
field countP = [Q2..0] ;
$define s0 'b' 000
$define s1 'b' 001
$define s2 'b' 010
$define s3 'b' 011
$define s4 'b' 100
$define s5 'b' 101
$define s6 'b' 110
$define s7 'b' 111
/* SYNCHRONOUS INPUT */
countP.sp = preset ;
countP.ar = reset ;
/* CLOCK ENABLER */
enable = start & L ;
/* STATE SEQUENCE */
sequence countP
{
present s0 if enable next s1; /* if enabler is high, the counter will go next state */
default next s0 ; /* else, counter will static on current state */
present s1 if enable next s2;
default next s1 ;
present s2 if enable next s3;
default next s2 ;
present s3 if enable next s4;
default next s3 ;
present s4 if enable next s5;
default next s4 ;
present s5 if enable next s6;
default next s5 ;
present s6 if enable next s7;
default next s6 ;
present s7 if enable next s0;
default next s7 ;
}