Logic circuits and timing diagrams were simulated using Deeds Simulator. This lab consists of 2 parts which are simulations of a given Boolean Expression and a problem-solving part which a circuit is required to be designed to solve the problem.

In part 1, I am required to simulate a basic gate Boolean Expression Y = AB + BC + AC using Deeds Simulator in both standard form and non-standard form. Then,  the timing diagram for each circuit was simulated for the comparison purpose.

In part 2, I was given a situation and was required to design a logic circuit to solve the problem. A series of steps were done and several logic circuits using basic gates and universal gates were designed and simulated. Then timing diagrams for each of the logic circuit were simulated too!

This lab introduces students about the development of a PLD device and a simple Hardware Description Language.

This project was done in pair with my partner HAM JING YI (A19EC0048). A Xerox machine was designed by implementing Count up Counter, Comparator & Clock Enabler on a GAL device. Program was generated using WinCUPL compiler to obtain a JEDEC file. The file is then programmed into the IC by using Wellon Programmer software. Lastly, the IC is tested by connecting it to a circuit by using ETS5000 training kit.