ETS for Digital Logic Lab 3
Video during Lab 3
Example Question for DL
A 3-bit count down ripple counter is designed using J-K flip-flop with negative edge triggered clock.
a) Draw the connection of logic symbol.
b) Draw the waveform outputs for 8 clock cycles.
c) Construct a state table for the counter.
d) Draw the state diagram the the counter.
Example Question for DL
A 2-bit count down ripple counter is designed using J-K flip-flop with negative edge triggered clock.
a) Draw the connection of logic symbol.
b) Draw the waveform outputs for 4 clock cycles.
c) Construct a state table for the counter.
d) Draw the state diagram the the counter.