Lab 2

Lab 2 is about combinational logic circuit design stimulation where creating a circuit using various logic gates are needed as well as generating the timing diagram for each circuit. Verifying the correct behaviour of the circuit and comparing simulation results with reasoning and concepts was also needed to complete this lab report.

                                           Figure 1: Basic logic gates circuit                                                                              Figure 2: Timing diagram for circuit in Figure 1

                                           Figure 3: Universal logic gates circuit                                                                              Figure 4: Timing diagram for circuit in Figure 3

Based on Figure 2 and 4, the results for the timing diagrams are the same, this shows that universal logic gates (NAND, NOR) could perform the functions and replace the basic gates (AND, OR, NOT).