FYP Logbook (Week 1 - Week 5)

Among the Final Year Project (FYP) titles that proposed and suggested by University, I had chosen some of the titles that I am interested to be my FYP title which of the following:

1. Traffic Light Detection
2. Design FPGA implementation of IIR filter for detecting QRS ECG signal
3. Built-In-Self-Test Design in PLC Processor

After a long consideration, finally I decided to choose “Design FPGA implementation of IIR filter for detecting QRS ECG signal” as my potential FYP title. I choose for this title because after I had done some of the research, I realized that this title is more related to the Matlab and Verilog RTL field which suits to my interested.

After some basics research based on the title, I know that QRS ECG signal is one of the most important signals in the field of medical science. A QRS complex is the most striking feature in ECG signal but the ECG signal are easily contaminated with noise which made it difficult to analyze them with naked eyes.

Therefore, this project aims to develop and design an implementation of IIR filter for detecting QRS ECG signal based on Field Programmable Gate Arrays (FPGAs).

For week 2, I had attended to the Online Research Methodology Workshop. The workshop is briefed about the Innovate Malaysia Design Competition by the speakers from various of the company for example, DreamCatcher, Intel and Keysight. All of the students were recommended to join for the event so that can get priority access to job vacancies after graduation from university that offered by participating companies.

Besides, I also think for the major deliverables and contributions of the project. I think that for my FYP title it can benefits the mankind which QRS complex is very useful in diagnosing cardiac arrhythmias, conduction abnormalities, and other diseases.

In order to ensure a smoother project flow, I had drafted for the purpose and end-goal for work, action that need to be taken in early stage and also major steps within the project plans.

Purpose and end-goal:

• The purpose of the work serve is to evolve a new ECG monitoring devices for health facilities with high accuracy in detection of irregular heartbeat for patience.

Action that needs to be taken in early stage:

• Study on other articles to get more ideas on designing the project.
• Study on the software that needed to use for the project
• Study on the programming language that will be used for the project. (C programming, Matlab Programming and Verilog RTL)

Major steps within project plans:

• Algorithm modelling using Matlab
• Debugging in Matlab
• Code hardware design using Vivado HLS
• Result verification in Vivado HLS
• RTL export from Vivado HLS
• Hardware implementation on FPGAs

In week 4, I continue to identify for the potential research problems, possible research question for each of the above problems and also the possible hypothesis for each of the above research question with the support of materials that can find in internet.

Problems:

1. Identify various of algorithm of detecting QRS ECG signal.
2. Code the Verilog HDL coding which required to build for the design.
3. Parallelism the algorithm so that it can be applied efficiently.

Question:

1. What software is suitable to use for modelling the algorithm of detecting QRS ECG signal?
2. How to make sure the correct functionality of the project in every procedure?
3. Why IIR filter is used for the project? What is it advantages compare with FIR?

Hypothesis:

1. Used Matlab to modelling the algorithm because it’s more user-friendly.
2. Testing and Debugging process need to be complete for every steps.
3. The advantage of IIR filters over FIR filters is that IIR filters usually require fewer coefficients to execute similar filtering operations means that IIR filters can work faster.

To get some background information on how others have tried to design the FPGA implementation of IIR filter for detecting QRS ECG filter, I have searched for some of the articles through internet.

For the 5 different article that are most related to my FYP titles are:

Article with titled Implementation of New QRS Detection Method based on FPGA, Zena Mohammed and Haider J.Abd (2020) mentioned that to diagnose heart disorders, different features should be extracted from EVG signal. This work presents a new method to improve ECG signal performance based on median filter and an automated R-peaks detection. The work was verified experimentally using field programmable gate array (FPGA). The proposed technique showed better performance and faster detection compare to the recent techniques at similar conditions.

Article with titled Designing & FPGA Implementation of IIR Filter Used for detecting clinical information from ECG, Manish Kansal, Hardeep Singh Saini and Dinesh Arora (2011) mentioned that the advantages of FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower cost than ASIC for moderate volume applications. Noise and interference are usually large enough to obscure small amplitude features of the ECG that are of physiological or clinical interest. The bandwidth of the noise overlaps that of wanted signals, so that simple filtering cannot sufficiently enhance the signal to noise ratio.

Article with titled De-noising of ECG signal on FPGA platform using digital filters, Sande Seema Bhogeshwar (2010) mentioned that Digital filter is the preeminent solution that caters to noise reduction up to a satisfactory level. Different Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filters are to be designed using MATLAB in order to check the feasibility of the specifications. Digital filters shall be designed in MATLAB to denoise the ECG signal with muscular noise and the performance will be evaluated based on error, accuracy and signal to noise ratio (SNR). Further the filters with the desired specifications are to be designed using Verilog Hardware Description Language (HDL).

Article with titled of FPGA Based Design And Implementation For Detecting Cardiac Arrhythmias, D.Hari Priya et al (2016) mentioned that the QRS complex being detected by 17 Hz band pass filter and shaped into a square pulse of 200ms width representing R peak by other circuitry is utilized in this work. Various arrhythmias are identified based on abnormalities in the time intervals between consecutive R peaks using Tompkins algorithm is presented. The algorithm is implemented in FPGA Spartan3.The algorithm is written in Verilog HDL and tested on Xilinx 13.1 ISE.

Article with titled of Real Time ECG Acquisition and FPGA Based QRS Detection, IEEE (2018) mentioned about the overall project is divided into two phases. First is to detect real time ECG signal the amplitude of the signal is very small so need design hardware in such a way that amplify and remove the artifacts from the signal and get proper ECG pattern. During second phase is about to denoise the signal first and then implements that with the FPGA. This system is useful to detect the heart beat by observing that rate and with the help of QRS complex it might be easily recognized situation of the heart.

After read and review through all the article above, I successfully get more information about my FYP title. I believe these knowledges might help me a lot while I am engage on the paperwork for my FYP.