FYP2 - EPORTFOLIO 5

           For FYP2 -EPORTFOLIO 5, this entry will explain on the results obtained with discussion. Few days before the submission journal, I finally managed to obtained all the results. Through this project, I gained a lot of experienced. Besides teaches me to be patient, keep the positive vibes and trust the process, despite I have to shifted the project to a new one in a short time.

        After the process of varying the channel dimensions, the next steps are extracting all the results generate from the SDEVICE tools and INSPECTION tools. The results are recorded and classified into 4 different tables based on the electrical properties which are threshold voltage (Vth), on-current (Ion), off-current (Ioff) and subthreshold slope (SS). To make it easier to observed and discuss the performances, the results are also being plotted by using MATLAB software. Figure 1, Figure 2, Figure 3 and Figure 4 shows the results in plotted form.

          The lower the Vth, the shorten conducting path flow overall reduces the time needed for the electrons to flow between the source and drain terminals. As shown in Figure 1, 10nm of channel dimension managed to achieved Vth at 0.54V and 0.47V when oxide thickness is 5nm and 8nm respectively. It can be seen that the lower the threshold voltage is achieved at the bigger the thickness of gate oxide which the lowest of Vth is achieved at 15nm channel dimension with oxide thickness, 8nm.

Figure 1: Threshold Voltage vs Gate Length

        The trend of oxide thickness for off-current shown in Figure 2, can be concluded that there is no much different of Ioff at 15nm, 25nm, 30nm, 40nm of gate length. However, at channel dimension below than 15nm, starts to show huge different. It is expected that the lower the channel dimension, the trends of off-current will shows in more significant effect. The results of on-current shows in Figure 3 that, at 30nm of channel dimension, the oxide thickness for both 5nm and 8nm, is achieved with the same value of on-current of 0.34mA. Further reducing channel dimension would lead to high leakage current. Therefore, to have better performances of the device, leakage current must be low. Thus, on current must be in high value in order to obtained high current ratio of Ion/Ioff. This will lead to a low leakage current.

Figure 2: Off-current vs Gate Length

Figure 3: On-current vs Gate Length

           Lastly, figure 4 shows the results of SS. SS is important because it affect the devices performances. This is because SS will define the ratio between the Ion and Ioff current. The increasing in SS will lowering the device performances of FD-SOI devices. Hence, SS must be decreases. As can be seen, from the plotted graph, SS is decreasing together when channel dimension is decreasing too. The lowest of SS is shown at 5nm of oxide thickness. Besides, starting at 30 nm of channel dimension and above, both oxide thickness doesn’t show much different of SS.

Figure 4: Subthreshold Slope vs Gate Length

           In conclusion, at channel dimension of 10nm with 5nm of oxide thickness provides the better performances of FD-SOI MOSFET. From the observations too, it can be seen that at 8nm of oxide thickness, the performances show a bit unstable compared to oxide thickness, 5nm. This is probably because of some effect, for instance, quantum effect occur that I don’t take account into. For future recommendation that can be improved from this project is by considering the channel concentration. I believe with this recommendation could improve the performance of FD-SOI MOSFET in semiconductor industry much better in future. Other than that, it is also important to take note that, even though we try to improve the performances in the devices, the fact that we cannot run from the SCE issues in semiconductor industry. However, we can help it by reducing the SCE issues.