FYP2 - EPORTFOLIO 4
End of April, the project of “Graphene-based Spin Logic Gates” had been shifted to a new title “Simulation Study On FD-SOI MOSFET Channel Dimension Variations Using TCAD.
For FYP2 -EPORTFOLIO 4, this entry will explain more on the methodology part used in this project. Synopsys Sentaurus TCAD Tools are used in order to run the simulation and the electrical properties. The methodology for this research project is shown below in Figure 1.
In order to build the structure of Fully-Depleted Silicon On Insulator (FD-SOI) MOSFET, first and foremost thing that need to do is validate the device parameter used. Validate process is very important in every structure as it will determine either the parameter fits the structure or not. As the transistor gets smaller, many parameters need to be considered. For instance, based on previous work, SiO2 is not applicable anymore to the gate insulator. It needs another high-k dielectric like HfO2. Based on the previous work done from the literature review finally, all the device parameters are obtained. The device parameters used to build the structure of FD-SOI which also used for the simulation is shown in Table 1 below. The device structure is then built-in the Sentaurus Device Editor (SDE) Tools.
Table 1: The device parameters of FD-SOI MOSFET.
| Device Parameters | Value (unit) |
| Channel Thickness, Hepi | 3-nm |
| BOX Thickness, HBOX | 10-nm |
| Spacer Length, Lsp | 25-nm |
| Gate Height, Hg | 15-nm |
| Substrate Thickness, Hsub | 30-nm |
| Total Length, Ltot | 100-nm |
| Gate Material | Gold |
| Gate Oxide Material | HfO2 |
| Work Function | 5.1 eV |
| Gate Voltage, Vg | 1.50 V |
| Drain Voltage, Vd | 0.05 V |
After the structure is completely developed, we need to vary the channel dimension to 5 different values which are Lg=10nm, Lg=15nm, Lg=25nm, Lg=30nm, and Lg=40nm. These variations of channel dimensions are chosen below 50nm. The reason is because, in the year 2020, it is expected the transistor is less than 5nm. Therefore, it is important to study the performances to at least 5 different values and the lowest channel dimension is at 10nm as we cannot directly start from 5nm.
Besides channel dimension is varied, oxide thickness also being varied to 5nm and 8nm. Oxide thickness also contributes to the performances of FD-SOI MOSFET. Therefore, to differentiate and study, oxide thickness is varying to 5nm and 8nm respectively. As the process of variation is done, the electrical properties are then generated through SDEVICE tools. The electrical properties that been observed are threshold voltage, on-current, off- current and subthreshold slope. All the results of the electrical properties are then recorded into the different tables and then being observed the performances.
Through the observations, it is shown that at channel dimension of 10nm and 5nm of oxide thickness shows the best performances of FD-SOI MOSFET.
Figure 1: The overall flowchart of the project.