FYP2 -EPORTFOLIO 3

       Last time, im working on silicon-based transistor and the result was i cannot get the right IV characteristics. The IV characteristic doesn’t follow the trends of MOSFET where it should be. Due to many problems, I decided to try another alternative. In order to optimize the performance, I tried to improve it by using Fully Depleted Silicon On Insulator (FDSOI). To an advantage, FDSOI can provide better short channel effect behaviour. The differences between FDSOI compared to silicon-based transistor was, FDSOI has one layer called buried oxide (BOX) as shown in figure 1 below. The BOX located it between silicon layer and silicon substrate. I have seen in the paper (references below), that it is possible to get IV characteristic when the gate length is reduced to below 50nm. Im working on it to make it possible too because im sure I can do it. Currently, im now on my way writing journal paper before submission on 11/6.

                                                                Figure 1:The structure of FDSOI

Reference:

1. R. Chau et al., "Silicon nano-transistors and breaking the 10 nm physical gate length barrier," in 61st Device Research Conference. Conference Digest (Cat. No. 03TH8663), 2003, pp. 123-126: IEEE.