Introduction
For the 3rd entry of my FYP2 progress report, according to the plan that I made during FYP1, I have started to design and simulate the standard cells using the Cadence Virtuoso tool.
Below here are my schematic designs and its simulation for the SAR ADC block and the ASC project conclusion
Progress 3
Reflection
For the ADC Block, I managed to design and simulate for the Digital-to-Analog (DAC) Block which is the R-2R Ladder DAC. The output values of the DAC approximately the same with the calculation using the DAC formula, with only 0.5% margin error.
However, for the SAR part, eventhough I have managed to design and simulating exactly as the original reference, I'm quite confused with the design that is being proposed by the reference, the Code/Sequence type, which only shows that it can shift bit but it cannot save the bit as expected, perhaps I need to use other reference (the Aldacher's Paper) which adjust the DFF by combining it with a multiplexer.
But it's cannot be finish in time, plus I have to give up on the Layout part due to my Schematics is still isn't complete, it's a bummer, so I had to focus on writing the report. All I can do is wish that if there are an opportunity to finish this project, I would try take it and finish it.