Introduction
For the 2nd entry of my FYP2 progress report, according to the plan that I made during FYP1, I have started to design and simulate the standard cells using the Cadence Virtuoso tool.
Below here are my schematic designs and its simulation for the DSC block
Progress 2
Reflection
I have successfully finished designing and simulating the DSC block, it is quite challenging but I've managed to do it. I have run the simulation and retrieved the simulation result of the DSC block, and it shows that DSC block does give the Stochastic Outputs based on the Digital Inputs. However, I have faced the difficulties in calculating the probability of ones in the Stochastic Outputs since it is in serial form which is different with the Digital Inputs which is in parallel form. Possible need to adjust the MLPCC to have parallel outputs, if I have the extra time to do so, but for now I must continue onto the next phase which is designing the Analog-to-Digital (ADC) Block.