Introduction
For the 1st entry of my FYP2 progress report, according to the plan that I made during FYP1, I have started to design and simulate the standard cells using the Cadence Virtuoso tool.
Below here are my schematic designs and its simulation for the standard cells.
Progress 1
Reflection
I have successfully finished designing and simulating the standard cells based on the knowledge that I have learnt from my prior class and the reference materials. Hopefully, I could continue onto the next part of the project which is designing the Digital-to-Stochastic Converter Block.