FYP 1 Progress Report Entry 3

This page mentioned the Final Year Project 1 Progress Report for Aidilfitri bin Sawalludin, A19EE0313

 

 

 

 

 

 

 

Introduction

For the 3rd entry of my FYP1 progress report, I have started doing a preliminary exercise of my FYP1.

 

In the preliminary exercise, I am designing, and simulating, some of the circuits that I will be using for FYP2 by using a simulation tool named LTSpice. This tool can help me design a schematic dan simulate the design with inputs that I have set. The circuits that I am designing and simulating, for now, are the D Flip-Flop and Digital Comparator. Below here are the schematic design and its simulation results.

Digital Comparator

The comparator part in the preliminary exercise has been designed as shown in Figure 2 exactly as the one that I am referring to. This digital comparator is supposedly capable to make comparison between two inputs, input A and input B, and produced the logical output based on which comparison that we want to do. There are 3 comparisons can be made; Output C is ‘1’ for when A<B; Output D is ‘1’ for when A=B, and Output E is ‘1’ for when A>B. The result in Figure 3 showcases that the design in Figure 2 behaved as expected as in Table 1.

Dig_Comp_Schem.jpg

Figure 2 1-Bit Comparator Logic Schematic Diagram

Dig_Comp_Wave.jpg

Figure 3 1-Bit Comparator Logic Waveform Result

Screenshot 2023-07-09 031740.png

D Flip-Flop (DFF)

Same case as in the comparator part, the D Flip-Flop has been designed as shown in Figure 4 exactly as the one that I am referring to. The logical D Flip-Flop is supposedly able to behave accordingly as shown in Table 2. To compare to the accuracy of the logical D Flip-Flop, another schematic using a built-in D Flip-Flop has been designed as shown in Figure 5 is already available in LTspice library and conducted the simulations for both circuits. The results of the simulations are shown in Figure 6 and it is found that the logical design of Figure 4 produced the same outputs as in the built-in design of Figure 5, which behaved exactly as Table 2.

 

DFF_Logic_Schem.jpg

Figure 4 D Flip-Flop with Set & Preset function Logic Schematic Diagram

DFF_LT_Schem.jpg

Figure 5 Built-in LTSpice D Flip-Flop with Set & Preset function Schematic Diagram

DFF_Wave.jpg

Figure 6 Waveform Results for both D Flip-Flop

Screenshot 2023-07-09 031751.png